Binary LMC - Little Man Computer Simulator

This is a Little Man Computer simulator. The original LMC uses denary instructions, but this uses binary to more closely model a real CPU. It has a 5 bit address bus and an 8 bit data bus. Instructions are 8 bits with direct addressing mode. Data are 8 bit signed integers in 2's-complement, between -128 and +127. Memory is limited to 32 x 8 bit slots for 32 bytes total memory.

Program in LMC assembly code:
  or CTRL+S
Pause after:
Share a link to your program in memory:

Binary LMC instruction set

Opcode Mnemonic Description
001xxxxx STA Store value from accumulator to memory address xxxxx
010xxxxx LDA Load value from memory address xxxxx into accumulator
011xxxxx ADD Add contents of memory address xxxxx to accumulator
100xxxxx SUB Subtract contents of memory address xxxxx from accumulator
101xxxxx BRA Branch to memory address xxxxx, unconditionally
110xxxxx BRZ Branch to memory address xxxxx if accumulator is zero
111xxxxx BRP Branch to memory address xxxxx if accumulator is positive (or zero)
00001--- INP Input from user into accumulator (--- not used)
00010--- OUT Output value of accumulator to the output box (--- not used)
00000--- HLT Terminates execution of the program
- DAT A memory location that contains data (an integer from -128 to 127)

The instruction set is the same as for the denary LMC - programs written in LMC assembly should work fine. Lines of assembly start with an optional label, then have one of the 11 mnemonics, then an optional value (which could be a denary integer or the name of a label defined on another line). Example program:

        INP         # user inputs a value
        STA   a     # which is stored into 'a'
        INP         # user inputs another value
        ADD   a     # which has 'a' added to it
        OUT         # and is then output
        HLT         # program terminates
    a   DAT         # ... location to store 'a'
    # Not used in this program...
    b   DAT   34    # put '34' in memory labelled 'b'

This simulator has a single R/W (read/write) signal for the control bus (real CPUs will have several more signals as part of this bus). The simulator's CPU has the same registers as in the OCR A level specification: